buffer circuit

The main electric circuit uses integration microprocessor and IC, few buffer circuit for stable operation.

主要功能电路采用集成度很高的单片机, 外围电路很少,工作更加稳定.

By reasonably using the special resources in FPGA, such as DCMs ( Digital Clock Manager) and BUFGMUXs ( global clock MUX buffer) and manually building up a proper clock circuit, the interference to timing caused by clock skew is mostly reduced.

通过合理使用DCM（数字时钟管理单元）和BUFG-MUX（全局时钟选择缓冲器）等FPGA的特殊资源，手动搭建时钟电路，可以尽可能地减少时钟偏差对电路时序的影响。

The data is sent to A/ D through conditioning circuit, and then it is sent into PC by FIFO buffer through EZ-USB. After algorithm conversion, the D/ A conversion outputs analog signal to carry out real-time control.

采集的数据经调理电路送A/D模数转换，再由FIFO缓存器经EZ-USB送上位机处理。经算法变换后的数据，由D/A转换输出模拟信号，实现实时控制。

Trace Buffer was widely applied in recording the historical track in the period of the programs' execution. And this convenience is used in many kinds of In-circuit Emulators and Oscilloscopes.

跟踪缓冲可以记录程序执行的历史轨迹，这在各种在线仿真器（ICE）和逻辑分析仪中得到了广泛的应用。

The RDC clamp buffer circuit is researched based on the solenoid valve control of industrial lockstitch sewing machine.

为此，基于高速工业平缝机的电磁阀控制，对钳位型RDC缓冲电路进行了研究。